BCM8426 ? 12-channel 1/2/4g fibre channel intelligent loop circuit with eyeopener? BCM8426 functional block diagram ? 12-channel intelligent loop circuit to configure fibre channel hard disk drives in fc-al loops integrated eyeopener p er channel exceeding fibre channel signalling specifications multi-rate support for new and legacy systems active-signal integrity (active-si) monitors physical layer and active-link integrity (active-li) monitors link-layer performance programmable transmit output levels and receive los detection high performance receive equalization and programmable transmit pre-emphasis developed using advanced 0.13u cmos process technology low-cost back end solution for fibre channel disk drive arrays guarantees jitter and bit-error-rate performance on optical and fiber links supports legacy 1.0625 gb and 2.125 gb applications, and new 4.25g data rates off a single reference clock frequency on-chip intelligent diagnostics provides insight to the signal quality with detect ion and recovery mechanisms on each high-speed link optimizes channel performance for lower power and signal detection through on-chip 2-wire control interface transmits and receives over long distances of copper cables or backplanes with 16 levels of programmable pre-emphasis low power design of ~4w with small footprint package in a 21 mm x 21 mm bga, with 1 mm ball pitch features summary of benefits disk0 BCM8426 intelligent loop circuit BCM8426 BCM8426 BCM8426 fc port fc port fc port fc port fc port fc port fc link 1.0625g, 2.125g, 4.25g fc port fc port fc port fc port fc port fc port additional ibod arrays fc link 1.0625g, 2.125g, 4.25g additional ibod arrays loop a loop b disk1 disk9 disk0 disk1 disk9 intelligent loop circuit intelligent loop circuit intelligent loop circuit
overview ? phone: 949-450-8700 fax: 949-450-8710 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 16215 alton parkway, p.o. box 57013 irvine, california 92619-7013 ? 2004 by broadcom corporation. all rights reserved. 8426-pb00-r 02/20/04 broadcom ? , the pulse logo, and connecting everything ? are trademarks of broadcom corporation and/ or its subsidiaries in the united states and certain other countries. all other trademarks mentioned are the property of their respective owners. the BCM8426 is an intelligent back end loop circuit that facilitates the implementation of an ibod (intelligent bunch of disks) on fibre channel storage array systems. the BCM8426 has an integrated eyeopener ? designed on-chip to drive optical and copper ports in fibre channel applications. each port of the BCM8426 can be independently configured as a retimer or repeater operating at the fibre channel data rates of 1.0625 gbps, 2.125 gbps, and 4.25 gbps. with an on-chip low- jitter phase-locked loop (pll), the BCM8426 exceeds fibre channel signal quality specifications. the BCM8426 features active signal integrity (active-si), which allows monitoring of the received signal at each high- speed port to determine signal eye quality and bit error rate (ber) for system diagnostics, fault isolation, optics aging, and maintenance. an on-chip pattern generator/checker is provided with internal loopback cap ability on each i/o port. the BCM8426 also features active link integrity (active-li), which is a set of advance link integrity functions performing data generation and checking on transmitted fibre channel data. the combination of active-si and active-li improves storage system?s reliability, availability, and serviceability (ras) with the ability to monitor and diagnose system integrity. data from each port can be optionally retimed utilizing an elastic fifo and local crystal reference clock eliminating jitter transfer. the BCM8426 can also be configured to operate in repeater mode for low latency. the BCM8426 is available in a 21 mm x 21 mm bga package. cdr cdr pll logic control power o0 i0 o1 i1 o2 i2 o3 i3 i10 o10 i9 o9 i8 o8 i11 o11 fref (106.25 mhz) dual 2-wire serial interface 1.2 v 3.3 v cdr cdr cdr cdr cdr cdr pbert active si active li o4 i4 cdr o5 i5 cdr i7 o7 cdr i6 o6 cdr cdr cdr pll logic control power o0 i0 o0 i0 o1 i1 o1 i1 o2 i2 o2 i2 o3 i3 o3 i3 i10 o10 i10 o10 i9 o9 i9 o9 i8 o8 i8 o8 i11 o11 i11 o11 fref (106.25 mhz) dual 2-wire serial interface 1.2 v 3.3 v cdr cdr cdr cdr cdr cdr pbert active si active li o4 i4 o4 i4 cdr o5 i5 o5 i5 cdr i7 o7 i7 o7 cdr i6 o6 i6 o6 cdr
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